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INTEGRATED CIRCUITS
DATA SHEET
PCD5090; PCA5097 DECT baseband controllers
Objective specification File under Integrated Circuits, IC17 1996 Oct 17
Philips Semiconductors
Objective specification
DECT baseband controllers
INTRODUCTION This data sheet details the specific features of the: PCD5090/xxx; DSP-ROM, with external ROM PCA5097/xxx; DSP-ROM, with Field Electronically Erasable Programmable Read Only Memory (FEEPROM).
PCD5090; PCA5097
* On-chip reference voltage FEATURES General * The PCx509x is designed for GAP-compliant handsets and simple base stations * Embedded 80C51 microcontroller with twice the performance of the classic architecture, up to 128 kbytes external memory or 64 kbytes FEEPROM program memory and 3 kbytes of data memory on chip. In addition there is 1 kbyte of on-chip data memory that is shared with on-chip Burst Mode Logic (BML) and DSP, the System Data RAM (SDR). * 80C51 ports P0, P1, P2 and P3 available for interfacing to display, keyboard, I2C-bus, interrupt sources and/or external memory. External program memory is addressable up to 128 kbytes (PCD5090/xxx and PCA5097/xxx). * Portable Part (PP) and Fixed Part (FP) modes * TDMA frame (de)multiplexing; transmission or reception can be programmed for any slot * Ciphering, scrambling, CRC checking/generation, protected B-fields * Speech and data buffering space for six handsets * Local call and B-field loop-back * Two interrupt lines for BML and DSP to interrupt 80C51 * On-chip, three-channel time-multiplexed 8-bit Analog-to-Digital Converter (ADC) for RSSI measurement and battery voltage measurement. One channel available for other purposes. * On-chip 8-bit DAC for frequency adjustment of 13.824 MHz on-chip crystal oscillator * Phase error measurement and phase error correction by hardware * Digital-to-Analog Converters (DACs) and ADCs for dynamic earpiece and dynamic or electret microphone * On-chip supply for electret microphone * Very low ohmic buzzer output * Serial interface to external ADPCM CODEC (PCD5032) * IOM-2interface (Siemens registered trademark) * Serial interface to synthesizer for frequency programming * Programmable timing of radio-control signals * Programmable polarity of radio-control signals * Easy interfacing with radio circuits, operating at other supply voltage * Programmable GMSK pulse shaper * On-chip comparator for use as bit-slicer * Power-on reset * Low supply voltage (2.7 to 5.5 V) * SACMOS technology. DSP software features * ADPCM encoding and decoding complying with G.721 * Speech filters * Programmable gain in speech paths * Side tone and soft mute * Ringer and tone (DTMF) generator * Dial tone detection * Echo cancellation * Automatic gain control * Telephone Answering Machine (TAM) switch * Conference call (PCD5090/400) * Hands-free operation (PCD5090/311). For each DSP software version a separate manual is available, in which detailed information is provided on how parameters must be set.
1996 Oct 17
2
Philips Semiconductors
Objective specification
DECT baseband controllers
ORDERING INFORMATION TYPE NUMBER PCD5090H PCA5097H PCD5090HZ PACKAGE NAME QFP100 LQFP100 DESCRIPTION
PCD5090; PCA5097
VERSION SOT317-2 SOT407-1
plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
1996 Oct 17
3
PCD5090; PCA5097
Objective specification
Fig.1 Functional blocks and signals in PCx509x.
handbook, full pagewidth
1996 Oct 17
PORT 1.0 to PORT 1.7 VSS_RF VDD_RF 2x VSS VSSA VDDA 2x VDD 8 8 8 PORT 2.0 to PORT 2.7 PORT 3.0 to PORT 3.7 8 PORT 1 PORT 3 IB-BUS PORT 2 digital pins analog pins supply pins VDD I2C-BUS AUX-RAM (3 kBYTES) MICROCONTROLLER_RAM (256 BYTES) TEST CONTROL BLOCK (TCB) TST1 TST2 AB-MICROCONTROLLER INTERFACE (ABCIF) SPEECH INTERFACE IOM/ADPCM (SPI)
VSS_FEE
VDD_FEE
PORT 0.0 to PORT 0.7
BLOCK DIAGRAM
VDD
PORT 0
Philips Semiconductors
PSE EA ALE
80CL51- CORE
PGM WEN SDI SC OEN SDO/A16
PGMFEE
FEEPROM (64 kBYTES)
MICROCONTROLLER
VDD_RF VDD BUZZER BUFFER (ABB) VDD VDDA VDD BZP BZM
DECT baseband controllers
VDD
DO DI FS1 DCK CLK3
LEVEL SHIFTER 4fs 1-BIT ADC ARD ARF ARA
BURST MODE LOGIC (BML) DIGITAL SIGNAL PROCESSOR (DSP) 4fs ATS 108fs 1-BIT ADC AMP DIGITAL DECIMATING FILTER (DDF) SYSTEM DATA RAM (SDR) (1 kBYTE)
DIGITAL NOISE SHAPER (DNS) 108fs
EARP EARM
4
CODEC
VDDA AUXILIARY ADC (AAD) ANALOG VOLTAGE REFERENCE (AVR) Vref ANALOG VOLTAGE SOURCE (AVS) MUX 3:1 VADC ISB BUS CONTROLLER (IBC) DIGITAL CONTROL OF ANALOG (DCA) POWER-ON RESET (POR) RESET GENERATOR (RGE) RESET_OUT M_RESET VBGP VANLO
LIFP LIFM MICP MICM VMIC CDC-on Vref
SLICE_CTR R_PWR R_ENABLE REF_CLK SYNTH_LOCK S_ENABLE S_CLK S_DATA VCO_BND_SW S_PWR ANT_SW0 ANT_SW1 T_ENABLE T_PWR_RMP T_DATA R_DATAP R_DATAM
R_SLICED
VDDA
T_GMSK
AGM
DPLL_DATA
GP_CLK7
VDD
CLOCK GENERATOR (CLG)
TIMING CONTROL BLOCK (TICB)
VANLI PEAK-HOLD RSSI_AN SUBTRACT VBAT Vref
XTAL1 XTAL2
XTAL OSCILLATOR (XOSC)
WATCHDOG TIMER (WDT)
CLK100
MGE610
EN_WATCHDOG
PINNING I/O O O O O O O O O I O O O O O - supply supply supply ISP2DRF3 ISP2DRF3 ANAIOD2 ANAIOD2 ISP2DRF3 ANAIOD1 ANAIOD1 ANAIOD1 ISP2DPES ISF2DPES ISF2UPES DIPP0PES - - O O I I O I I I O I/O I - input L - - - H - - H L - - - running ISP4DRF3 H ISP2DRF3 switch synthesizer power output 13.824 MHz reference clock for synthesizer output negative supply voltage for RF interface level shifters positive supply voltage for RF interface level shifters positive supply voltage for FEEPROM program memory switch slicer time constant output switch receiver power output positive input for receiver data negative input for receiver data enable receiver output analog input for RSSI measurement analog input to A/D converter analog input for battery voltage measurement 3.456 MHz clock output for external ADPCM codec ADPCM output or IOM data clock input/output (ISF2UPES in PCD5090/xxx, PCA5097/xxx) ADPCM or IOM data input L ISP2DRF3 L ISP2DRF3 serial synthesizer data output clock for serial synthesizer interface output L ISP2DRF3 synthesizer enable output - DIPP0RF3 synthesizer lock input L ISP2DRF3 VCO band switch output L ANAIOD1 GMSK modulated transmitter data output off ISF2DRF3 unmodulated transmitter data output L ISP2DRF3 switch transmitter power output H ISP2DRF3 enable transmitter output H ISP2DPES 100 Hz signal related to DECT frame timing output H ISP2DRF3 antenna switch 0 output H ISP2DRF3 antenna switch 1 output PIN TYPE PIN DESCRIPTION
PIN
SYMBOL
1996 Oct 17 STATE AFTER RESET
QFP100
LQFP100
ANT_SW1
1
99
Philips Semiconductors
ANT_SW0
2
100
CLK100
3
1
T_ENABLE
4
2
T_PWR_RMP
5
3
T_DATA
6
4
T_GMSK
7
5
DECT baseband controllers
VCO_BND_SW
8
6
SYNTH_LOCK
9
7
S_ENABLE
10
8
S_DATA
11
9
S_CLK
12
10
S_PWR
13
11
5
REF_CLK
14
12
VSS_RF
15
13
VDD_RF
16
14
VDD_FEE
17
15
SLICE_CTR
18
16
R_PWR
19
17
R_DATAP
20
18
R_DATAM
21
19
R_ENABLE
22
20
RSSI_AN
23
21
VANLI
24
22
VBAT
25
23
CLK3
26
24
DCK
27
25
PCD5090; PCA5097
Objective specification
DI
28
26
PIN I/O I/O O O I O I I I I - supply ANAIOR1 ANAIOR1 ANAIOD1 ANAIOD1 ANAIOR1 supply ANAIOD1 ANAIOD1 DIUP0PES ISQ2CPES ISQ2CPES ISQ2CPES ISP2DPES ISP2DPES ISP2DPES DIDP0PES ISQ2CPES ISQ2CPES H ISQ2CPES reference voltage (+2 V) bandgap output voltage (+1.25 V) positive supply voltage for analog circuits negative output to earpiece positive output to earpiece watchdog enable input bidirectional 80C51 port pin bidirectional 80C51 port pin bidirectional 80C51 port pin general purpose 6.912 MHz output data after clock recovery network R_DATA comparator output FEEPROM programming mode; can be left open-circuit for PCA5090 and PCD5090/xxx bidirectional 80C51 port pin bidirectional 80C51 port pin bidirectional 80C51 port pin positive input from microphone positive microphone supply voltage (+2 V) negative input from microphone negative supply voltage for analog circuits I I O O O - O O I I/O I/O I/O O O O I I/O I/O I/O H H - L L L H H H - 1.4 V 1.4 V - 1.25 V 2.0 V off 0.7 V 0.7 V - 0.7 V ANAIOD1 positive input from line interface 0.7 V ANAIOD1 negative input from line interface - DIDP0PES test input 1 - DIDP0PES test input 2 1.0 V ANAIOD1 analog output from D/A converter - ANAIOD1 crystal oscillator input running ANAIOD1 crystal oscillator output off ISI8DPES ADPCM or IOM data output input ISF2DPES ISF2UPES 8 kHz framing input/output (ISF2UPES in PCD5090/xxx, PCA5097/xxx) PIN TYPE PIN DESCRIPTION
SYMBOL
1996 Oct 17 STATE AFTER RESET
QFP100
LQFP100
FS1
29
27
DO
30
28
Philips Semiconductors
XTAL2
31
29
XTAL1
32
30
VANLO
33
31
TST2
34
32
TST1
35
33
LIFM
36
34
DECT baseband controllers
LIFP
37
35
VSSA
38
36
MICM
39
37
MICP
40
38
VMIC
41
39
6
Vref
42
40
VBGP
43
41
VDDA
44
42
EARM
45
43
EARP
46
44
EN_WATCHDOG
47
45
P1.0
48
46
P1.1
49
47
P1.2
50
48
GP_CLK7
51
49
DPLL_DATA
52
50
R_SLICED
53
51
PGM
54
52
P1.3
55
53
PCD5090; PCA5097
P1.4
56
54
Objective specification
P1.5
57
55
PIN I/O I/O I/O - supply ANAIOD2 ANAIOD2 supply supply ISQ2CPES ISQ2CPES ISQ2CPES ISQ2CPES ISQ2CPES ISQ2CPES ISQ2CPES ISQ2CPES ISQ2CPES ISQ2CPES ISQ2CPES ISP4DPES bidirectional 80C51 port pin bidirectional 80C51 port pin bidirectional 80C51 port pin PCA5090,PCA5097: FEEPROM shift data output PCD5090/xxx, PCA5097/xxx: FEEPROM shift data out/address bit 16 for 128 kbytes external program memory FEEPROM output enable; tie to VDD for PCA5090, PCD5090/xxx FEEPROM shift clock; can be left open-circuit for PCA5090, PCD5090/xxx FEEPROM shift data input; can be left open-circuit for PCA5090, PCD5090/xxx FEEPROM Write enable; can be left open-circuit for PCA5090, PCD5090/xxx ISQ2CPES ISQ2CPES bidirectional 80C51 port pin bidirectional 80C51 port pin bidirectional 80C51 port pin bidirectional 80C51 port pin bidirectional 80C51 port pin bidirectional 80C51 port pin bidirectional 80C51 port pin bidirectional 80C51 port pin bidirectional 80C51 port pin bidirectional 80C51 port pin negative supply voltage negative supply voltage positive buzzer output negative buzzer output positive supply voltage O O - - I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O H or L L - DIDP0PES DIDP0PES DIDP0PES DIUP0PES - - - H H H H H H H H H H H H H - - L L - off ISI8DPES bidirectional 80C51 port pin off ISI8DPES bidirectional 80C51 port pin PIN TYPE PIN DESCRIPTION
SYMBOL
1996 Oct 17 STATE AFTER RESET
QFP100
LQFP100
P1.6
58
56
P1.7
59
57
Philips Semiconductors
VDD2
60
58
BZM
61
59
BZP
62
60
VSS2
63
61
VSS_FEE
64
62
P3.0
65
63
DECT baseband controllers
P3.1
66
64
P3.2
67
65
P3.3
68
66
P3.4
69
67
P3.5
70
68
P3.6
71
69
7 I I I I I/O I/O
P3.7
72
70
P2.0
73
71
P2.1
74
72
P2.2
75
73
SDO/A16
76
74
OEN
77
75
SC
78
76
SDI
79
77
WEN
80
78
P2.3
81
79
PCD5090; PCA5097
Objective specification
P2.4
82
80
PIN I/O I/O I/O I/O O O I - supply supply ISP2DPES ISQ2CPES ISP2DPES ISQ2CPES ISP2DPES ISQ2CPES ISP2DPES ISQ2CPES ISP2DPES ISQ2CPES ISP2DPES ISQ2CPES ISP2DPES ISQ2CPES ISP2DPES ISQ2CPES DIDP0PES ISF2DPES bidirectional 80C51 port pin (ISQ2CPES in PCD5090/xxx, PCA5097/xxx) bidirectional 80C51 port pin (ISQ2CPES in PCD5090/xxx, PCA5097/xxx) bidirectional 80C51 port pin (ISQ2CPES in PCD5090/xxx, PCA5097/xxx) bidirectional 80C51 port pin (ISQ2CPES in PCD5090/xxx, PCA5097/xxx) bidirectional 80C51 port pin (ISQ2CPES in PCD5090/xxx, PCA5097/xxx) bidirectional 80C51 port pin (ISQ2CPES in PCD5090/xxx, PCA5097/xxx) bidirectional 80C51 port pin (ISQ2CPES in PCD5090/xxx, PCA5097/xxx) master reset input (Schmitt-trigger) reset output bidirectional 80C51 port pin (ISQ2CPES in PCD5090/xxx, PCA5097/xxx) positive supply voltage negative supply voltage - I/O I/O I/O I/O I/O I/O I/O I/O I O H - off H off H off H off H off H off H off H off H - - - ISF2DPES external access enable (80C51) H ISQ4CPES address latch enable (80C51) H ISQ2CPES program store enable (80C51) H ISQ2CPES bidirectional 80C51 port pin H ISQ2CPES bidirectional 80C51 port pin H ISQ2CPES bidirectional 80C51 port pin PIN TYPE PIN DESCRIPTION
SYMBOL
1996 Oct 17 STATE AFTER RESET
QFP100
LQFP100
P2.5
83
81
P2.6
84
82
Philips Semiconductors
P2.7
85
83
PSE
86
84
ALE
87
85
EA
88
86
VSS1
89
87
VDD1
90
88
DECT baseband controllers
P0.7
91
89
P0.6
92
90
P0.5
93
91
8
P0.4
94
92
P0.3
95
93
P0.2
96
94
P0.1
97
95
P0.0
98
96
M_RESET
99
97
PCD5090; PCA5097
RESET_OUT
100
98
Objective specification
Philips Semiconductors
Objective specification
DECT baseband controllers
PCD5090; PCA5097
100 RESET_OUT
99 M_RESET
90 VDD1 89 VSS1
98 P0.0
97 P0.1
96 P0.2
95 P0.3
94 P0.4
93 P0.5
92 P0.6
91 P0.7
85 P2.7
84 P2.6
83 P2.5
82 P2.4
handbook, full pagewidth
ANT_SW1 ANT_SW0 CLK100 T_ENABLE T_PWR_RMP T_DATA T_GMSK VCO_BND_SW SYNTH_LOCK
1 2 3 4 5 6 7 8 9
81 P2.3 80 79 78 77 76 75 74 73 72 71 70 69 68 67
86 PSE
87 ALE
88 EA
WEN SDI SC OEN SDO/A16 P2.2 P2.1 P2.0 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 VSS_FEE VSS2 BZP BZM VDD2 P1.7 P1.6 P1.5 P1.4 P1.3 PGM R_SLICED DPLL_DATA GP_CLK7
S_ENABLE 10 S_DATA 11 S_CLK 12 S_PWR 13 REF_CLK 14 VSS_RF 15 VDD_RF 16 VDD_FEE 17 SLICE_CTR 18 R_PWR 19 R_DATAP R_DATAM R_ENABLE RSSI_AN VANLI VBAT CLK3 DCK DI FS1 DO 20 21 22 23 24 25 26 27 28 29 30 XTAL2 31 XTAL1 32 VANLO 33 TST2 34 TST1 35 LIFM 36 LIFP 37 VSSA 38 MICM 39 MICP 40 VMIC 41 Vref 42 VBGP 43 VDDA 44 EARM 45 EARP 46 EN_WATCHDOG 47 P1.0 48 P1.1 49 P1.2 50
PCA5097 PCD5090
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
MGE575
Fig.2 Pin configuration of PCX509x (QFP100).
1996 Oct 17
9
Philips Semiconductors
Objective specification
DECT baseband controllers
PCD5090; PCA5097
98 RESET_OUT
100 ANT_SW0
97 M_RESET
99 ANT_SW1
88 VDD1
87 VSS1
78 WEN
96 P0.0
95 P0.1
94 P0.2
93 P0.3
92 P0.4
91 P0.5
90 P0.6
89 P0.7
83 P2.7
82 P2.6
81 P2.5
80 P2.4
79 P2.3
84 PSE
85 ALE
77 SDI
handbook, full pagewidth
CLK100 T_ENABLE T_PWR_RMP T_DATA T_GMSK VCO_BND_SW SYNTH_LOCK S_ENABLE S_DATA
1 2 3 4 5 6 7 8 9
76 SC 75 OEN 74 SDO/A16 73 P2.2 72 P2.1 71 P2.0 70 P3.7 69 P3.6 68 P3.5 67 P3.4 66 P3.3 65 P3.2 64 P3.1 63 P3.0 62 VSS_FEE 61 VSS2 60 BZP 59 BZM 58 VDD2 57 P1.7 56 P1.6 55 P1.5 54 P1.4 53 P1.3 52 PGM 51 R_SLICED DPLL_DATA 50
MGD744
S_CLK 10 S_PWR 11 REF_CLK 12 VSS_RF 13 VDD_RF 14 VDD_FEE 15 SLICE_CTR 16 R_PWR 17 R_DATAP 18 R_DATAM 19 R_ENABLE 20 RSSI_AN 21 VANLI 22 VBAT 23 CLK3 24 DCK 25 P1.0 46 P1.1 47 P1.2 48 EN_WATCHDOG 45 GP_CLK7 49 DI 26 FS1 27 DO 28 XTAL2 29 XTAL1 30 VANLO 31 TST2 32 TST1 33 LIFM 34 LIFP 35 VSSA 36 MICM 37 MICP 38 VMIC 39 Vref 40 VBGP 41 VDDA 42 EARM 43 EARP 44
PCD5090
Fig.3 Pin configuration of PCD5090/xxx only (LQFP100).
1996 Oct 17
10
86 EA
Philips Semiconductors
Objective specification
DECT baseband controllers
FUNCTIONAL DESCRIPTION DECT controller system description The PCX509x is a family of single-chip controllers, designed for use in Digital Enhanced Cordless Telecommunications (DECT) systems. The family is designed for minimal component-count and minimum power consumption. All controllers include an embedded 80C51 microcontroller with on-chip memory and I2C-bus. The Philips DECT RF-Interface is implemented. The Burst Mode Logic performs the time-critical MAC layer functions for applications in DECT handsets and base stations. The ADPCM transcoding is in compliance with the CCITT recommendation G.721 and includes receive and transmit filters. Power-on reset logic and power management functions further reduce power consumption and external components. The chip is intended to support stand-alone systems only. There are no provisions to build clusters of base stations. There are no provisions for external controllers to exert control over the embedded 80C51 or to have direct access to the on-chip data memories. The DECT controller consists of a number of functional blocks that operate more or less autonomously and communicate with each other via the System Data RAM (SDR). Blocks have access to SDR via the Internal System Bus (ISB). The ISB consists of an 8-bit data, a 10-bit address bus and a number of bus-request/bus-grant signals. Access to the ISB is controlled by ISB bus Controller (IBC). The IBC acknowledges bus requests on the basis of a priority scheme. The embedded controller 80C51 is to be programmed by the user. It must contain DECT software from Man-Machine-Interface (MMI) to the DECT protocols TBC, CBC and DBC (refer to figures 10, 11, 12 and 13 in "prETS 300 175-2:1992 section 6"). All software is available from Philips Semiconductors. Hardware state machines in the Burst Mode Logic (BML) and the Speech Interface (SPI) execute the lower blocks in the TBC, CBC and DBC. The 80C51 has control over the BML and the SPI via tables in SDR. The BML saves serial data, received via R_DATAP/M, in buffer areas in SDR. The position of buffers in SDR is fixed by the 80C51 software by means of tables previously mentioned.
PCD5090; PCA5097
A-fields and B-fields are stored in separate buffers. In this way, two traffic bearers, each with their private A-fields, can share the same B-field buffer as is required in case of bearer hand-over or local call. The blocks DSP and CODEC support speech processing functions such as A/D- and D/A conversion, filtering, ADPCM encoding and decoding, 8-bit A-law PCM to 14-bit linear PCM conversion and its reverse, echo cancelling, tone generation, etc. PCA5097 This chip is intended for program development. It contains 64 kbytes of internal program memory (FEEPROM) for the 80C51 and DSP program RAM. PCD5090/xxx This chip is intended for handset and base station applications. The DSP program is now fixed in a ROM, for which several ROM codes (/xxx) are available (handset, analog base, digital base). An external program memory for the 80C51 of 128 kbytes ROM can be handled. PCA5097/xxx This is the same as PCD5090/xxx, but there is 64 kbytes internal program memory (FEEPROM) for the 80C51. The DSP program is preprogrammed in ROM. This chip is meant for development purpose only.
1996 Oct 17
11
Philips Semiconductors
Objective specification
DECT baseband controllers
PCD5090; PCA5097
handbook, full pagewidth
EARPIECE RADIO CIRCUITS PCx509x MICROPHONE
MGE586
a. Handset.
handbook, full pagewidth
RADIO CIRCUITS
PCx509x
LINE INTERFACE (e.g. PCD1070)
a/b line
MGD745
b. Base with analog interface and echo cancellation; up to 6 portables can be handled.
handbook, full pagewidth
EARPIECE RADIO CIRCUITS PCx509x MICROPHONE 2 2 x IOM or 2 x ADPCM-CODEC or a combination
MGD746
c. Base with digital interface and analog handset connected; up to 6 portables can be handled.
Fig.4 Block diagrams of DECT systems with PCx509x.
1996 Oct 17
12
Philips Semiconductors
Objective specification
DECT baseband controllers
PACKAGE OUTLINES
PCD5090; PCA5097
QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT317-2
c
y X
80 81
51 50 ZE
A
e E HE A A2 A1
Q (A 3) Lp L detail X
wM pin 1 index bp 100 1 wM D HD ZD B vM B 30 vMA 31
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.40 0.25 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.65 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 Q 1.4 1.2 v 0.2 w 0.15 y 0.1 Z D (1) Z E(1) 0.8 0.4 1.0 0.6 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT317-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1996 Oct 17
13
Philips Semiconductors
Objective specification
DECT baseband controllers
PCD5090; PCA5097
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SOT407-1
c
y X 75 76 51 50 ZE A
e E HE wM bp L pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X A A2
Q A1 (A 3) Lp
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.5 1.3 A3 0.25 bp 0.28 0.16 c 0.18 0.12 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 Q 0.70 0.57 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7 0o
o
16.25 16.25 15.75 15.75
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-12-19
1996 Oct 17
14
Philips Semiconductors
Objective specification
DECT baseband controllers
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all LQFP and QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering
PCD5090; PCA5097
Wave soldering is not recommended for LQFP or QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions: * Do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). * Do not consider wave soldering QFP packages QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Oct 17
15
Philips Semiconductors
Objective specification
DECT baseband controllers
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Short-form specification Limiting values
PCD5090; PCA5097
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. The data in this specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Oct 17
16

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